View K9WBG08U1M-ICB00_3792297.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flash memory 1 k9kag08u0m k9wbg08u1m k9ncg08u5m k9xxg08xxm * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
flash memory 2 k9kag08u0m k9wbg08u1m k9ncg08u5m document title 2g x 8 bit / 4g x 8 bit / 8g x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 1.0 remark advance preliminary final history 1. initial issue 1. add random data output after read for copy 2. add read for copy-back with data output timing guide 3. modify 2-plane copy-back program operation 4. modify 2kb program operation timing guide 1. interleave two plane copy- back program timing is added. 2. qdp lga package is added. 3. tcsd is changed. (10ns -> 0ns) draft date dec, 26th 2006 feb. 2nd 2007 mar. 31st 2007
flash memory 3 k9kag08u0m k9wbg08u1m k9ncg08u5m general description features ? voltage supply - 3.3v device(k9xxg08uxm) : 2.7v ~ 3.6v ? organization - memory cell array : (2g + 64m) x 8bit - data register : (4k + 128) x 8bit ? automatic program and erase - page program : (4k + 128)byte - block erase : (256k + 8k)byte ? page read operation - page size : (4k + 128)byte - random read : 25 s(max.) - serial access : 25ns(min.) * k9ncg08u5m : 50ns(min.) ? fast write cycle time - page program time : 200 s(typ.) - block erase time : 1.5ms(typ.) 2g x 8 bit / 4g x 8 bit / 8g x 8 bit nand flash memory ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology -endurance : 100k program/erase cycles ( with 1bit/512byte ecc) - data retention : 10 years ? command driven operation ? intelligent copy-back with internal 1bit/528byte edc ? unique id for copyright protection ? package : - k9kag08u0m-pcb0/pib0 : pb-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) - k9wbg08u1m-pcb0/pib0 : pb-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) - k9wbg08u1m-icb0/iib0 52 - pin tlga (12 x 17 / 1.0 mm pitch) - k9mcg08u5m-pcb0/pib0 : pb-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) offered in 2gx8bit, the k9kag08u0m is a 16g-bit nand flash memory with spare 512m-bit. the device is offered in 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state application market. a program operation can be performe d in typical 200 s on the (4k+128)byte page and an erase operation can be performed in typical 1.5ms on a (256k+8k)byte block. data in the data register can be read out at 25ns(k9ncg08u5m: 50ns) cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write controller automates all progr am and erase functions includin g pulse repetition, where required, and internal verification and ma rgining of data. even the write-intensive systems can take ad van- tage of the k9kag08u0m s extended reliability of 100k program /erase cycles by providing ecc( error correcting code) with real time mapping-out algorithm. the k9kag08u0m is an optimum solution for large nonvolatile storage applications such as solid stat e file storage and other portable appl ications requiring non-volatility. an ultra high density solution having two 16gb stacked with two ch ip selects is also available in standard 32gb tsopi package a nd another ultra high density solution having two 32g b tsopi package stacked with four chip selects is also available in 64gb tsop i- dsp. product list part number vcc range organization pkg type k9kag08u0m-p 2.7v ~ 3.6v x8 tsop1 k9wbg08u1m-p k9wbg08u1m-i 52tlga k9ncg08u5m-p tsop1-dsp
flash memory 4 k9kag08u0m k9wbg08u1m k9ncg08u5m pin configuration (tsop1) k9kag08u0m-pcb0/pib0 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c
flash memory 5 k9kag08u0m k9wbg08u1m k9ncg08u5m pin configuration (tsop1) k9wbg08u1m-pcb0/pib0 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c k9wbg08u1mn.c
flash memory 6 k9kag08u0m k9wbg08u1m k9ncg08u5m 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 1.0 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 k9wbg08u1m- icb0 / iib0 52-tlga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1 r/b2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 ? ab c m 0.1 ? ab c m 0.1 package dimensions
flash memory 7 k9kag08u0m k9wbg08u1m k9ncg08u5m 18.80 max ref 12.40 max ref 0.13~0.23 pin #1 #1 #24 #48 0.50 typ #25 (0.10) a (0.249) basic gage plane 0.399~0.600 20.00 0.20 0.02 min 2.35 max typ both sides bottom tsop only (0.10) a -a- seating pin configuration (tsop1-dsp) k9ncg08u5m-pcb0/pib0 package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin tsop1 dual stacked package 12mm x 20mm n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c r/b4 r/b3 ce3 ce4
flash memory 8 k9kag08u0m k9wbg08u1m k9ncg08u5m pin description note connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. there are two ce pins (ce 1 & ce 2 ) in the k9wbg08u1m and four ce pins (ce 1 & ce 2 & ce 3 & ce 4 ) in the k9ncg08u5m. there are two r/b pins (r/b 1 & r/b 2) in the k9wbg08u1mk9wbg08u1mk9ncg08u5m and four r/b pins (r/b 1 & r/b 2 & r/ b 3 & r/b 4) in the k9ncg08u5m. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce / ce 1 chip enable the ce / ce 1 input is the device selection control. when the device is in the busy state, ce / ce 1 high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce / ce 1 control during read operation , refer to ?page read? section of device operation. ce 2 chip enable the ce 2 input enables the second k9k8g08u0a re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protecti on during power transitions. the internal high volt- age generator is reset when the wp pin is active low. r/b / r/b 1 ready/busy output the r/b / r/b 1 output indicates the status of the device oper ation. when low, it indicates that a program, erase or random read operation is in process and retu rns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
flash memory 9 k9kag08u0m k9wbg08u1m k9ncg08u5m 4k bytes 128 bytes figure 1. k9kag08u0m functional block diagram figure 2. k9kag08u0m array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 *l *l *l 3rd cycle a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 20 4th cycle a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 28 5th cycle a 29 a 30 a 31 *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 13 - a 31 a 0 - a 12 command ce re we cle wp i/0 0 i/0 7 v cc v ss 512k pages (=8,192 blocks) 4k bytes 8 bit 128 bytes 1 block = 64 pages (256k + 8k) byte i/o 0 ~ i/o 7 1 page = (4k + 128)bytes 1 block = (4k + 128)b x 64 pages = (256k + 8k) bytes 1 device = (4k+128)b x 64pages x 8,192 blocks = 16,896 mbits row address page register ale 16,384m + 512m bit nand flash array (4,096 + 128)byte x 524,288 y-gating row address column address column address row address data register & s/a
flash memory 10 k9kag08u0m k9wbg08u1m k9ncg08u5m product introduction the k9kag08u0m is a 16,896mbit(17,716,740,096 bit) memory organi zed as 524,288 rows(pages) by 4,224x8 columns. spare 128x8 columns are located from column address of 4,096~4,223. a 4,224-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 32 cells that are serially connected to fo rm a nand structure. each of the 32 cells resides in a different page. a block consists of two nand structured strings. a nand structur e consists of 32 cells. total 2,162,688 nand cells reside in a bl ock. the program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memor y array consists of 8,192 separately erasabl e 256k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9kag08u0m. the k9kag08u0m has addresses multiplexed into 8 i/os. this sc heme dramatically reduces pi n counts and allows system upgrades to future densities by maintaining cons istency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively , via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for ex ecution. the 2,112m byte physical spa ce requires 32 addresses, thereby requiring five cy cles for addressing : 2 cycles of column address, 3 cycles of row address, in t hat order. page read and page program need the same five address cycl es following the required comm and input. in block erase oper- ation, however, only the three row address cycles are used. device operations are selected by writing specific commands into th e command register. table 1 defines the specific commands of the k9kag08u0m. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the exter nal buffer memory. since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
flash memory 11 k9kag08u0m k9wbg08u1m k9ncg08u5m table 1. command sets note : 1. random data input/output can be executed in a page. 2. any command between 11h and 80h/81h/85h is prohibited except 70h/f1/f2 and ffh. 3. read edc status is only available on copy back operation. 4. interleave-operation between two chips is allowed. it?s prohibited to use f1h and f2h commands for other operations except interleave-operation. 5. two-plane random data output msut be used after two-plane read operation caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - two-plane page read 60h----60h 30h two-plane read for copy-back 60h----60h 35h reset ffh - o page program 80h 10h page program with 2kb data 80h----11h 80h----10h two-plane page program 80h---11h 81h---10h copy-back program 85h 10h copy-back program with 2kb data 85h----11h 85h----10h two-plane copy-back program (2) 85h---11h 81h---10h block erase 60h d0h two-plane block erase 60h---60h d0h random data input (1) 85h - random data output (1) 05h e0h two plane random data output (1), (5) 00h----05h e0h read status 70h o read edc status (3) 7bh o chip1 status (4) f1h o chip2 status (4) f2h o
flash memory 12 k9kag08u0m k9wbg08u1m k9ncg08u5m k9kag08u0m is arranged in four 4gb memory planes. each plane c ontains 2,048 blocks and 4,224 byte page registers. this allows it to perform simultaneous page program and block erase by select ing one page or block from each plane. the block address map i s configured so that two-plane program/erase/read operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. for example, two-plane program/erase/read operation into plane 0 and plane 2 is prohibited. that is to say, two-plane program/e rase/ read operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed memory map plane 0 plane 1 plane 2 plane 3 (2048 block) (2048 block) (2048 block) (2048 block) page 0 page 1 page 63 page 62 block 0 page 0 page 1 page 63 page 62 block 1 page 0 page 1 page 63 page 62 block 4096 page 0 page 1 page 63 page 62 block 4097 page 0 page 1 page 63 page 62 block 4094 page 0 page 1 page 63 page 62 block 4095 page 0 page 1 page 63 page 62 block 8190 page 0 page 1 page 63 page 62 block 8191 4224byte page registers 4224byte page registers 4224byte page registers 4224byte page registers page 0 page 1 page 63 page 62 block 2 page 0 page 1 page 63 page 62 block 3 page 0 page 1 page 63 page 62 block 4098 page 0 page 1 page 63 page 62 block 4099 page 0 page 1 page 63 page 62 block 4092 page 0 page 1 page 63 page 62 block 4093 page 0 page 1 page 63 page 62 block 8188 page 0 page 1 page 63 page 62 block 8189
flash memory 13 k9kag08u0m k9wbg08u1m k9ncg08u5m recommended operating conditions (voltage reference to gnd, k9xxg08uxm-xcb0 : t a =0 to 70 c, k9xxg08uxm-xib0 : t a =-40 to 85 c) parameter symbol k9xxg08uxm(3.3v) unit min typ. max supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transit ions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to vss v cc -0.6 to + 4.6 v v in -0.6 to + 4.6 v i/o -0.6 to vcc + 0.3 (< 4.6v) temperature under bias k9xxg08uxm-xcb0 t bias -10 to +125 c k9xxg08uxm-xib0 -40 to +125 storage temperature k9xxg08uxm-xcb0 t stg -65 to +150 c k9xxg08uxm-xib0 short circuit current i os 5 ma dc and operating characteristics (recommended operating conditions otherwise noted.) note : 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2. typical value is measured at v cc =3.3v, ta=25 c. not 100% tested. 3. the typical value of the k9wbg08u1m?s i sb 2 is 40 a and the maximum value is 200 a. 4. the typical value of the k9ncg08u5m?s i sb 2 is 80 a and the maximum value is 400 a. 5. the maximum value of k9wbg08u1m-p?s i li and i lo is 40 a, the maximum value of k9wag08u1m-i?s i li and i lo is 20 a . 6. the maximum value of k9ncg08u5m?s i li and i lo is 80 a. parameter symbol test conditions k9xxg08uxm unit 3.3v min typ max operating current page read with serial access i cc 1 trc=25ns, (k9ncg08u5m: trc=50ns) ce =v il, i out =0ma -2535 ma program i cc 2- erase i cc 3- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc - 20 100 a input leakage current i li v in =0 to vcc(max) - - 20 output leakage current i lo v out =0 to vcc(max) - - 20 input high voltage v ih (1) - 0.8x vcc - vcc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2x vcc output high voltage level v oh i oh =-400 a2.4-- output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b )v ol =0.4v 8 10 - ma
flash memory 14 k9kag08u0m k9wbg08u1m k9ncg08u5m valid block note : 1. the device may include initial invalid blocks when first shi pped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of inva lid blocks considered. invalid bloc ks are defined as blocks that contain one or more bad bits. do not erase or pro- gram factory-marked bad blocks. refer to the attached technical notes for appr opriate management of invalid blocks. 2. the 1st block, which is plac ed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with 1 bit/512byte ecc. 3. the number of valid blocks is on the basis of single pla ne operations, and this may be de creased with two plane operations. * : each k9kag08u0m chip in the k9wbg08u1m and k9ncg08u5m has maximum 160 invalid blocks. parameter symbol min typ. max unit k9kag08u0m n vb 8,032 - 8,192 blocks k9wbg08u1m n vb 16,064* - 16,384* blocks k9ncg08u5m n vb 32,128* - 32,768* blocks ac test condition (k9xxg08xxm-xcb0 :t a =0 to 70 c,k9xxg08xxm-xib0:t a =-40 to 85 c,k9xxg08uxm: vcc=2.7v ~ 3.3v, unless otherwise noted) parameter k9xxg08uxm input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf (k9kag08u0m-p, k9wbg08u1m-i) 1 ttl gate and cl=30pf (k9wbg08u1m-p, k9ncg08u5m-p) mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input lllh x data output x x x x h x during read(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by capacitance ( t a =25 c, v cc =3.3v , f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. k9wbg08u1m-ixb0?s capacitance(i/o, input) is 10pf. item symbol test condition min max unit k9kag08u0m k9wbg08u1m k9ncg08u5m input/output capaci- c i/o v il =0v - 10 20 40 pf input capacitance c in v in =0v - 10 20 40 pf
flash memory 15 k9kag08u0m k9wbg08u1m k9ncg08u5m program / erase characteristics note : 1. typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 2. typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature . parameter symbol min typ max unit program time t prog - 200 700 s dummy busy time for two-plane page program t dbsy -0.51 s number of partial program cycles nop - - 4 cycles block erase time t bers -1.52 ms ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding control pins must occur only once while we is held low 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min max unit k9ncg08u5m k9kag08u0m k9ncg08u5m k9kag08u0m k9wbg08u1m k9wbg08u1m cle setup time t cls (1) 25 12 - - ns cle hold time t clh 10 5 - - ns ce setup time t cs (1) 35 20 - - ns ce hold time t ch 10 5 - - ns we pulse width t wp 25 12 - - ns ale setup time t als (1) 25 12 - - ns ale hold time t alh 10 5 - - ns data setup time t ds (1) 20 12 - - ns data hold time t dh 10 5 - - ns write cycle time t wc 45 25 - - ns we high hold time t wh 15 10 - - ns address to data loading time t adl (2) 100 100 - - ns
flash memory 16 k9kag08u0m k9wbg08u1m k9ncg08u5m ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit k9ncg08u5m k9kag08u0m k9ncg08u5m k9kag08u0m k9wbg08u1m k9wbg08u1m data transfer from cell to register t r --2525 s ale to re delay t ar 10 10 - ns cle to re delay t clr 10 10 - ns ready to re low t rr 20 20 - ns re pulse width t rp 25 12 - ns we high to busy t wb - - 100 100 ns read cycle time t rc 50 25 - - ns re access time t rea - - 30 20 ns ce access time t cea - - 45 25 ns re high to output hi-z t rhz - - 100 100 ns ce high to output hi-z t chz - - 30 30 ns ce high to ale or cle don?t care t csd 10 10 - - - re high to output hold t rhoh 15 15 - - ns re low to output hold t rloh -5- -ns ce high to output hold t coh 15 15 - - ns re high hold time t reh 15 10 - - ns output hi-z to re low t ir 00 - -ns re high to we low t rhw 100 100 - - ns we high to re low t whr 60 60 - - ns device resetting time(read/ program/erase) t rst -- 5/10/500 (1) 5/10/500 (1) s wp high to we low t ww 100 100 - - ns
flash memory 17 k9kag08u0m k9wbg08u1m k9ncg08u5m nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial invalid block inform ation. devices with initial in valid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid bl ock(s) does not affect the performance of valid bl ock(s) because it is isolated from the bi t line and the common source line by a sele ct tran- sistor. the system design must be able to mask out the initial in valid block(s) via address mappi ng. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycl es with 1bit/512byte ecc. all device locations are erased(ffh) except locations where the initial invalid block( s) information is written prior to shippi ng. the ini- tial invalid block(s) status is defined by the 1st byte in t he spare area. samsung makes sure that either the 1st or 2nd page o f every initial invalid block has non-ffh data at the column address of 4096. since the initial invalid block information is also era sable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recogniz e the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(figure 3). any intentional erasure of t he original initial invalid block information is prohibited. * check "ffh" at the column address 4096 figure 3. flow chart to create initial invalid block table start set block address = 0 check "ffh" increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table
flash memory 18 k9kag08u0m k9wbg08u1m k9ncg08u5m nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation r esults in an error, map out the block including the page in error and copy the target data to another block. * error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following possible failure modes shoul d be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replac ement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacem ent can be executed with a page-si zed buffer by finding an erased empty block and reprogramming the current target data and copying t he rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of me mory space, it is recommended that the r ead or verification failure due to single bit error be reclaimed by ecc without any block replac ement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure ve rify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 19 k9kag08u0m k9wbg08u1m k9ncg08u5m erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program block ?a? by creating an ?i nvalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2
flash memory 20 k9kag08u0m k9wbg08u1m k9ncg08u5m nand flash technical notes (continued) copy-back operation with edc & sector definition for edc generally, copy-back program is very powerful to move data stor ed in a page without utilizing any external memory. but, if the source page has one bit error due to charge loss or charge gain, then wi thout edc, the copy-back program operation could also accumula te bit errors. k9kag08u0m supports copy-back with edc to prevent cumulati ve bit errors. to make edc valid, the page program operation should be performed on either whole page(4224byte) or sector(528byte). modifying the data of a sector by random data input before copy-back program must be performed for the whole sector and is allowed only once per each sector. any partial modification smaller than a sector corrupts the on-chip edc codes. a 4,224-byte page is composed of 8 sectors of 528-byte and eac h 528-byte sector is composed of 512-byte main area and 16-byte spare area. "a" area 512 byte (1?st sector) main field (4,096 byte) "i" (1?st ) 16 "b" area 512 byte (2?nd sector) "c" area 512 byte (3?rd sector) "d" area 512 byte (4?th sector) spare field (128 byte) table 2. definition of the 528-byte sector sector main field (column 0~2,047) spare field (column 2,048~2,111) area name column address area name column address 1?st 528-byte sector "a" 0 ~ 511 "i" 4,096 ~ 4,111 2?nd 528-byte sector "b" 512 ~ 1,023 "j" 4,112 ~ 4,127 3?rd 528-byte sector "c" 1,024 ~ 1,535 "k" 4,128 ~ 4,143 4?th 528-byte sector "d" 1,536 ~ 2,047 "l" 4,114 ~ 4,159 5?th 528-byte sector "e" 2,048 ~ 2,559 "m" 4,160 ~ 4,175 6?th 528-byte sector "f" 2,560 ~ 3,071 "n" 4,176 ~ 4,191 7?th 528-byte sector "g" 3,072 ~ 3,583 "o" 4,192 ~ 4,207 8?th 528-byte sector "h" 3,584 ~ 4,095 "p" 4,208 ~ 4,223 "e" area (5?th sector) "f" area (6?th sector) "g" area (7?th sector) "h" area (8?th sector) "j" (2?nd ) "k" (3?rd ) "l" (4?th ) "m" (5?th ) "n" (6?tht ) "o" (7?th ) "p" (8?th ) 512 byte 512 byte 512 byte 512 byte byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte
flash memory 21 k9kag08u0m k9wbg08u1m k9ncg08u5m within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is th e lsb among the pages to be programmed. therefore, lsb doesn?t need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 addressing for program operation : : : : interleave page program k9kag08u0m is composed of two k9f8g08u0ms. k9kag08u 0m provides interleaving operation between two k9f8g08u0ms. this interleaving page program improves the system throughput almost twice compared to non-interleaving page program. at first, the host issues page program command to one of the k9f8g08u0m chips, say k9f8g08x0m(chip #1). due to this k9kag08u0m goes into busy state. during this time, k9f8g08u0m(c hip #2) is in ready state. so it can execute the page program command issued by the host. after the execution of page program by k9f8g08u0m(chip #1) , it can execute another page program regardless of the k9f8g08u0m(chip #2). before that the host needs to check the status of k9f8g08u0m(chip #1) by issuing f1h command. only when the status of k9f8g08u0m(chip #1) becomes ready status, host can issue another page program command. if the k9f8g08u0m(chip #1) is in busy state, the host has to wa it for the k9f8g08u0m(chip #1) to get into ready state. similarly, k9f8g08u0m chip(chip #2) can execute another page pr ogram after the completion of the previous program. the host can monitor the status of k9f8g08u0m(chip #2) by issuing f2h co mmand. when the k9f8g08u0m(chip #2) shows ready state, host can issue another page program command to k9f8g08u0m(chip #2). this interleaving algorithm improves the system throughput al most twice. the host can issue page program command to each chip individually. this reduces the time lag for the completion of operation. note: during interleave operations, 70h command is prohibited.
flash memory 22 k9kag08u0m k9wbg08u1m k9ncg08u5m r/ b (#1) busy of chip #1 i/o x 80h 10h command a 31 : low add & data 80h 10h a 31 : high add & data busy of chip #2 internal only r/b (#2) internal only r/b interleave page program f1h or f2h ab c d another page program on chip #1 state a : chip #1 is executing a page program operation and chip #2 is in ready state. so the host can issue a page program command to ch ip #2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is terminated, but page program on chip #2 is still operating. and t he system should issue f1h comman d to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another page program command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate page program on chip #1 and chip #2 alternately. status operation status command / data f1h f2h a chip 1 : busy, chip 2 : ready 8xh cxh b chip 1 : busy, chip 2 : busy 8xh 8xh c chip 1 : ready, chip 2 : busy cxh 8xh d chip 1 : ready, chip 2 : ready cxh cxh
flash memory 23 k9kag08u0m k9wbg08u1m k9ncg08u5m r/ b (#1) busy of chip #1 i/o x 60h d0h command a 31 : low add 60h d0h a 31 : high add busy of chip #2 internal only r/b (#2) internal only r/b interleave block erase f1h or f2h ab c d another block erase on chip #1 state a : chip #1 is executing a block erase operation, and chip #2 is in ready state. so the host can issue a block erase command to chi p #2. state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is term inated, but block erase on chip #2 is still oper ating. and the system should issue f1h command to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another block erase command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate block erase on chip #1 and chip #2 alternately. status operation status command / data f1h f2h a chip 1 : busy, chip 2 : ready 8xh cxh b chip 1 : busy, chip 2 : busy 8xh 8xh c chip 1 : ready, chip 2 : busy cxh 8xh d chip 1 : ready, chip 2 : ready cxh cxh
flash memory 24 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) t dbsy i/o x command t prog of chip #1 internal only r/b (#2) internal only r/b 81h 10h a 31 :low add & data 80h 11h a 31 : low add & data f1h or f2h* 81h 10h a 31 :high add & data 80h 11h a 31 : high add & data t dbsy t prog of chip #2 r/nb (#1) i/o x internal only r/b (#2) internal only r/b t prog of chip #2 1 1 interleave two-plane page program state a : chip #1 is executing a page program operation, and chip #2 is in ready state. so the host can issue a page program command to c hip #2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is completed and chip #1 is ready for the next operation. chip #2 is still executing page program oper ation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next page program command to chip #1. f2h command is required to check the status of chip #2 to issue the next page program command to chip #2. according to the above process, the system can operate tw o-plane page program on chip #1 and chip #2 alternately. ab cd
flash memory 25 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) i/o x command t bers of chip #1 internal only r/b (#2) internal only r/b 60h d0h a 31 :low add 60h a 31 : low add f1h or f2h* 60h d0h a 31 :high add 60h a 31 : high add t bers of chip #2 t bers of chip #2 1 1 interleave two-plane block erase r/b (#1) i/o x internal only r/b (#2) internal only r/b ab c state a : chip #1 is executing a block erase operati on, and chip #2 is in ready state. so the host can issue a block erase command to chi p #2. state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is completed and ch ip #1 is ready for the next operation. chip #2 is still executing block erase operat ion. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next block erase command to chip #1. f2h command is required to check the st atus of chip #2 to issue the nex t block erase command to chip #2. as the above process, the system can operate two-pl ane block erase on chip #1 and chip #2 alternatively. d
flash memory 26 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) i/o x command internal only r/b (#2) internal only r/b f1h or f2h* 1 1 interleave read to page program operation r/b (#1) i/o x internal only r/b (#2) internal only r/b ab c state a : chip #1 is executing a page program operation, and chip #2 is in ready state. so the host can issue a read command to chip #2. state b : both chip #1 is executing page program oper ation and chip #2 is executing read operation. state c : read operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing page program op eration. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check t he status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave read to page porgram on chip #1 and chip #2 alternatively. d 10h 80h a 31 : low add data in t prog of chip #1 30h 00h a 31 : high add data out t r of chip #2 t prog of chip #1
flash memory 27 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 interleave copy-back program operation ab state a : chip #1 is executing a copy-back program operation, and chip #2 is in ready state. so the host can issue a read for copy-back c ommand to chip #2. state b : both chip #1 is executing copy-back program operatio n and chip #2 is executing read for copy-back operation. state c : read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing c opy-back program operation. state d : both chip #1 and chip #2 are ready. state e : chip #2 is executing a copy-back program operation, and chip #1 is in ready state. so the host can issue a read for copy-back c ommand to chip #1. state f : both chip #2 is executing copy-back program operati on and chip #1 is executing read for copy-back operation. state c : read for copy-back operation on chip #1 is completed and chip #1 is ready for the next operation. chip #2 is still executing c opy-back program operation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check t he status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave copy-back program on chip #1 and chip #2 alternatively. 10h 85h a 31 : low add t prog of chip #1 35h 00h a 31 : high add t r of chip #2 command f1h or f2h* c r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 df 10h 85h a 31 : high add 35h 00h a 31 : low add command f1h or f2h* g t prog of chip #2 t r of chip #1 e h
flash memory 28 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) i/o x tr internal only r/b (#2) internal only r/b 60h a 31 : low add 1 1 interleave two-plane copy back program r/b (#1) i/o x internal r/b (#2) internal r/b a a 19 : low a 31 : low a 19 : high a 31 : low a 19 : low a 31 : low a 19 : high tprog of chip #1 only only a 31 : low a 19 : low a 31 : low a 19 : high 60h add 35h 00h add 05h add e0h data out 00h add 05h add e0h data out 85h add 11h tdbsy 81h add 10h 60h a 31 : high add a 19 : low a 31 : high a 19 : high 60h add 35h a 31 : high a 19 : low 00h add 05h add e0h data out 2 tr
flash memory 29 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b (#1) i/o x command internal r/b (#2) internal r/b f1h or f2h* 3 2 interleave two-plane copy back program r/b (#1) i/o x internal r/b (#2) internal r/b b c state a : chip #1 is executing a page program operation, and chip #2 is in ready state. so the host can issue a page program command to c hip #2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is completed and chip #1 is ready for the next operation. chip #2 is still executing page program oper ation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next page program command to chip #1. f2h command is required to check the status of chip #2 to issue the next page program command to chip #2. according to the above process, the system can operate tw o-plane page program on chip #1 and chip #2 alternately. tprog of chip #2 only only a 31 : high a 19 : high 00h add 05h add e0h data out a 31 : high a 19 : low a 31 : hgih a 19 : high 85h add 11h 81h add 10h only only tprog of chip #1 tprog of chip #2 3 d tdbsy
flash memory 30 k9kag08u0m k9wbg08u1m k9ncg08u5m system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or seri al access as shown below. the internal 4,224byte data registers are utilized as separate buf fers for this operation and the system desig n gets more flexible. in addition, for v oice or audio applications whic h use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox
flash memory 31 k9kag08u0m k9wbg08u1m k9ncg08u5m command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 k9kag08u0m i/o 0 ~ i/o 7 4,224byte a0~a7 a8~a12 a13~a20 a21~a28 a29~a31 i/ox ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls
flash memory 32 k9kag08u0m k9wbg08u1m k9ncg08u5m input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t coh t rhz i/ox t chz t rhz notes : 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 33mhz. trhoh starts to be valid when frequency is lower than 33mhz.
flash memory 33 k9kag08u0m k9wbg08u1m k9ncg08u5m status read cycle & edc status read cycle ce we cle re 70h/7bh status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz t chz serial access cycle after read (edo type, cle=l, we =h, ale=l) t rhoh t coh t rloh dout dout t rea notes : 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 33mhz. trhoh starts to be valid when frequency is lower than 33mhz. f1/f2
flash memory 34 k9kag08u0m k9wbg08u1m k9ncg08u5m read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 row add3 row add3 t clr t csd t csd t coh
flash memory 35 k9kag08u0m k9wbg08u1m k9ncg08u5m random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h/35h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 e0h t rhw t clr t whr t rea
flash memory 36 k9kag08u0m k9wbg08u1m k9ncg08u5m page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr
flash memory 37 k9kag08u0m k9wbg08u1m k9ncg08u5m page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl 2. for edc operation, only one time random data input is possible at the same address. t adl t whr i/o 0 =0 successful program i/o 0 =1 error in program
flash memory 38 k9kag08u0m k9wbg08u1m k9ncg08u5m copy-back program operation with random data input ce cle r/b we ale re 00h i/o x 85h column address row address read edc status or read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 row add3 row add3 70h/7bh i/o 1 ~ i/o 2 : edc status (7bh only) notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl 2. for edc operation, only one time random data input is possible at the same address. t whr
flash memory 39 k9kag08u0m k9wbg08u1m k9ncg08u5m block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr
flash memory 40 k9kag08u0m k9wbg08u1m k9ncg08u5m 00h column address tw row address a 13 ~a 20 a 21 ~a 28 a 29 ~a 31 a 8 ~a 12 a 0 ~a 7 twc column address a 8 ~a 12 a 0 ~a 7 05h dout n 00h column address tw row address a 13 ~a 20 a 21 ~a 28 a 29 ~a 31 a 8 ~a 12 a 0 ~a 7 twc column address a 8 ~a 12 a 0 ~a 7 05h e0h dout m 60h tw row address a 13 ~a 20 a 21 ~a 28 a 29 ~a 31 twc 60h tw row address a 13 ~a 20 a 21 ~a 28 a 29 ~a 31 twc 30h 1 1 ce cle r/b we ale re i/ox ce cle r/b we ale re i/ox busy t wb t r t rea t whr t clr t whr t clr t rea e0h t rc t rc dout n+1 t rhw dout m+1 a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 0 ~ a 12 : valid a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid a 31 : valid a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 two-plane page read operation with two-plane random data out
flash memory 41 k9kag08u0m k9wbg08u1m k9ncg08u5m two-plane page program operation 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h t prog col add1,2 & row add 1,2,3 4224 byte data ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h i/o program confirm command (true) 81h 70h page row address i/ox 1 up to 4224 byte data serial input din m read status command t dbsy : typ. 500ns max. 1 s col add1 col add2 row add1 row add2 row add3 col add1 col add2 row add1 row add2 row add3 col add1,2 & row add 1,2,3 4224 byte data a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid note: any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. note twhr a 31 : valid a 31 : must be same as previous a 31 i/o 0 = 0 successful erase i/o 0 = 1 error in erase twb tprog
flash memory 42 k9kag08u0m k9wbg08u1m k9ncg08u5m two-plane block erase operation block erase setup command1 erase confirm command read status command 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers ex.) address restriction for tw o-plane block erase operation ce cle r/b i/o x we ale re 60h row add1 d0h 70h i/o 0 busy t wb t bers t wc d0h 70h address address row add1,2,3 i/o 0 = 0 successful erase i/o 0 = 1 error in erase row add2 row add3 a 13 ~ a 18: fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address t whr a 31 : valid a 31 : must be same as previous a 31
flash memory 43 k9kag08u0m k9wbg08u1m k9ncg08u5m read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle k9kag08u0m d5h 51h a6h 68h k9wbg08u1m same as k9kag08u0m in it k9ncg08u5m device 4th cyc. code 3rd cyc. 5th cyc.
flash memory 44 k9kag08u0m k9wbg08u1m k9ncg08u5m 4th id data description i/o7 i/o6 i/o5 i/ i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 id definition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, number of simultaneously programmed pages, etc page size, block size,redundant area size, organization, serial access minimum plane number, plane size 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1
flash memory 45 k9kag08u0m k9wbg08u1m k9ncg08u5m 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0
flash memory 46 k9kag08u0m k9wbg08u1m k9ncg08u5m device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. therefore only five address cycles and 30h command init iates that operation after initial power up. the 4,224 bytes of data within the selected page are transferred to the data registers in less than 20 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25ns(k9nc08u5m:50ns) cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox
flash memory 47 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 7. random data output in a page address 00h data output r/b re t r 30h/35h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 page program the device is programmed basically on a page basis, but it does allow multiple partia l page programming of a word or consecutiv e bytes up to 4,224, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 ti mes for a single page. the addressing should be done in sequent ial order in a block. a page program cycle consists of a serial data loading period in which up to 4,224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the data other than those to be prog rammed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. modifying the data of a sector by random data input before copy-back program must be performed for the whole sector and is allowed only once per each sector. any partial modification smaller than a sector corrupts the on-chip edc codes. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status commands and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are no t successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" col. add.1,2
flash memory 48 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 9. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" copy-back program the copy-back program is configured to qu ickly and efficiently rewrite data stored in one page without utilizing an external me mory. since the time-consuming cycles of serial access and re-loading cycles ar e removed, the system performance is improved. the ben - efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly a ssigned free block. the operation for performing a copy-back program is a sequential execution of page-read without serial access and c opy- ing-program with the address of destination page. a read operati on with "35h" command and the address of the source page moves the whole 4,224-byte data into the internal data buffer. as soon as the device returns to ready state, page-copy data-input com - mand (85h) with the address cycles of destination page followed may be written. the program confirm command (10h) is required t o actually begin the programming operation. during tprog, the device executes edc of itself. once the program process starts, the read status register command (70h) or read edc status command (7bh) may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. when the copy-back program is complete, the write status bit(i/o 0) and edc status bits (i/o 1 ~ i/o 2) may be checked(figure 10 & figure 11& figure 12& figure 13& figure 14). the internal write verification detects only errors for "1"s that are not succes sfully programmed to "0"s and the internal edc chec ks whether there is only 1-bit error for ea ch 528-byte sector of the source page. m ore than 2-bit error detection is not available for each 528-byte se ctor. the command register remains in read status command mode or read edc status command mode until another valid command is written to the command register. during copy-back program, data modification is possible using random data input comma nd (85h) as shown in figure11. but edc status bits are not available during copy back for some bits or bytes modified by random data input operation. however, in case of the 528 byte sector uni t modification, edc status bits are available. figure 10. page copy-back program operation 00h r/b add.(5cycles) i/o0 pass 85h 70h/7bh fail t prog add.(5cycles) t r source address destination address 35h 10h i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 figure 11. page copy-back program operation with random data input 00h r/b add.(5cycles) 85h 70h t prog add.(5cycles) t r source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 note: 1. for edc operation, only one time random data input is possible at the same address. note : copy-back program operation is allo wed only within the same memory plane. "0" "1"
flash memory 49 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 12. page copy-back program operation with edc & read edc status 00h r/b add.(5cycles) 85h 7bh t prog add.(5cycles) t r source address destination address 35h 10h i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 edc status output figure 14. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accomplished in thr ee cycles initiated by an erase setup command(60h). only address a 19 to a 31 is valid while a 13 to a 18 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal eras ing process. this two-step sequence of se tup followed by execution command ensures t hat memory contents are not accidentally eras ed due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bi t(i/o 0) may be checked. figure 14 details the sequence. 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h fail t bers i/ox "0" "1" edc operation note that for the user who use copy-back with edc mode, only one time random data input is possible at the same address during copy-back program or page program mode. fo r the user who use copy-back without edc, there is no limitation for the random data input at the same address. figure 13. two-plane page copy-back program operation with edc & read edc status r/b 85h 7bh t prog add.(5cycles) destination address 11h i/ox col. add.1,2 & row add.1,2,3 edc status output 60h r/b add.(3cycles) t r source address i/ox row add.1,2,3 35h 60h add.(3cycles) source address row add.1,2,3 81h add.(5cycles) destination address 10h col. add.1,2 & row add.1,2,3 t dbsy
flash memory 50 k9kag08u0m k9wbg08u1m k9ncg08u5m two-plane page read two-plane page read is an extension of page read, for a single plane with 4,224 byte page regist ers. since the device is equipp ed with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of two pages. two-plane page read is initiated by repeating command 60h followed by three address cy cles twice. in this case only same page of same block ca n be selected from each plane. after read confirm command(30h) the 8,448 bytes of data within the selected two page are transferred to the data registers in l ess than 25us(tr). the system controller can detect the completi on of data transfer(tr) by monitoring the output of r/b pin. once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with fiv e address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences. the restricti ons for two-plane page program are shown in figure 15. two-plane read must be used in the block which has been progr ammed with two-plane page program. figure 15. two-plane page read operation with two-plane random data out 60h i/o x r/b 60h 30h t r address (3 cycle) address (3 cycle) a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid two-plane page program two-plane page program is an extension of page program, for a si ngle plane with 4,224 byte page registers. since the device is equipped with two memory planes, activating the two sets of 4, 224 byte page registers enables a simultaneous programming of two pages. after writing the first set of data up to 4,224 byte into the selected page register, dummy page program command (11h) instead of actual page program command (10h) is inputted to finish data-loadi ng of the first plane. since no programming process is involv ed, r/b remains in busy state for a short period of time(tdbsy). r ead status command (70h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). then the next set of data for the other plane is inputted a fter the 81h command and address sequences. after inputting data for the la st plane, actual true page program(10h) instead of dummy page program command (11h) must be followed to star t the programming process. the operation of r/b and read status is the same as that of page program. althougth two planes are progra mmed simultaneously, pass/fail is not available for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two-pl ane page program is shown is figure16. a 31 : must be same as previous a 31 a 31 : valid a 31 : must be same as previous a 31 a 31 : must be same as previous a 31
flash memory 51 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 16. two-plane page program 80h 11h data input plane 0 (2048 block) block 0 block 2 block 4094 block 4092 note :1. it is noticeable that same physically row address is applied to the two blocks 81h 10h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 31 : valid a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30: valid a 31 : must be same as previous a 31 2. any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. note* 2 note : it is an example for two-plane page program into plane 0~1(in this case, a 30 is low), and the method for two-plane page program into plane 2 ~3 is same. two-plane page program into plane 0&2( or plane 0&3, or plane 1&2, or plane 1&3) is prohibited. 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog address & data input pass 70h i/o0 fail "0" "1"
flash memory 52 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 17. two-plane copy-back program operation two-plane copy-back program two-plane copy-back program is an extension of copy-back program, for a single plane with 4,224 byte page registers. since the device is equipped with two memory planes, ac tivating the two sets of 4,224 byte page registers enables a simultaneous program- ming of two pages. r/b 85h 70h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 31 : must be same as previous a 31 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 31 : must be same as previous a 31 1 note2 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 1 row add.1,2,3 row add.1,2,3 a 31 : valid a 31 : must be same as previous a 31 note : 1. copy-back program operation is allowed only within the same memory plane. 2 . any command between 11h and 81h is prohibited except 70h/f1h and ffh.
flash memory 53 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 18. two-plane copy-back program operation with random data input r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 1 2 2 destination address destination address note : 1. copy-back program operation is allo wed only within the same memory plane. 2. on the same plane, it?s prohibited to oper ate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). therefore, the copy-back program is permitted just between odd address pages or even address pages. 3 . any command between 11h and 81h is prohibited except 70h/f1h and ffh. note3 a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 31 : must be same as previous a 31 a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 31 : must be same as previous a 31 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 1 row add.1,2,3 row add.1,2,3 a 31 : valid a 31 : must be same as previous a 31
flash memory 54 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 19. two-plane block erase operation 60h i/o x r/b 60h d0h i/o0 pass fail t bers address (3 cycle) address (3 cycle) 70h "0" "1" a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid two-plane block erase basic concept of two-plane block erase operati on is identical to that of two-plane p age program. up to two blocks, one from eac h plane can be simultaneously erased. standard block erase comm and sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. only one block should be selected from each pla ne. the erase confirm command(d0h) initiates the actual erasi ng process. the completion is detected by monitoring r/b pin or ready/ busy status bit (i/o 6). two-plane erase operations can be execut ed by dividing the memory array into plane 0~1 or plane 2~3 separately. for example, two-plane erase operation into plane 0 and plane 2 is pr ohibited. that is to say, two-plane erase operation into p lane 0 and plane 1 or into plane 2 and plane 3 is allowed. a 31 : valid a 31 : must be same as previous a 31 note : two-plane block erase into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
flash memory 55 k9kag08u0m k9wbg08u1m k9ncg08u5m read status table 3. status register definition for 70h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1" the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. afte r writing 70h or f1h/f2h command to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 3 fo r specific 70h status regist er definitions and table 4 for specific f1h/f2h status register definiti ons. the command register remains in status read mode until further commands are issue d to it. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before start ing read cycles. table 4. f1h/f2h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect prote cted : "0" not protected : "1"
flash memory 56 k9kag08u0m k9wbg08u1m k9ncg08u5m read edc status read edc status operation is only availabl e on ?copy back program?. t he device contains an edc stat us register which may be read to find out whether there is error during ?read for copy back?. after writing k9kag08u0m command to the command register, a read cycle outputs the content of the edc status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to t able 5 for specific status register definitions. the command register remains in edc status read mode until further commands are issued to it. table 5. status register definition for 7bh command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. 2. more than 2-bit error det ection isn?t avail able for each 528 byte sector. that is to say, only 1- bit error detection is avalia ble for each 528 byte sector. i/o copy back program page program block erase read definition i/o 0 pass/fail of copy back program pass/fai l pass/fail not use pass : "0", fail : "1" i/o 1 edc status not use not use not use no error : "0", error : "1" i/o 2 validity of edc status not use not use not use valid : "1", invalid : "0" i/o 3 not use not use not use not use don?t -cared i/o 4 not use not use not use not use don?t -cared i/o 5 not use not use not use not use don?t -cared i/o 6 ready/busy of copy back program ready/busy ready/busy ready/busy busy : "0", ready : "1" i/o 7 write protect of copy back program write protect write protect write protect protected : "0", not protected :"1"
flash memory 57 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 20. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(e ch), and the device code and 3rd, 4th, 5th cycle id respective ly. the command register remains in read id mode until further commands are issued to it. figure 20 shows the operation sequence. t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle k9kag08u0m d5h 51h a6h 68h k9wbg08u1m same as k9kag08u0m in it k9ncg08u5m
flash memory 58 k9kag08u0m k9wbg08u1m k9ncg08u5m figure 21. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. w hen the device is in busy state during ran dom read, program or erase mode, the reset operation will abort t hese operations. the contents of me mory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 21 below. ffh i/o x r/b t rst table 5. device status after power-up after reset operation mode 00h command is latched waiting for next command
flash memory 59 k9kag08u0m k9wbg08u1m k9ncg08u5m ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it return s to high when the internal controller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obt ained with the following reference chart(fig.22). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp ibusy c l busy ready vcc voh tf tr vol 3.3v device - v ol : 0.4v, v oh : 2.4v figure 22. rp vs tr ,tf & rp vs ibusy tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l
flash memory 60 k9kag08u0m k9wbg08u1m k9ncg08u5m data protection & power up sequence the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before inter nal circuit gets ready for any command sequences as shown in figure 23. the two step co mmand sequence for program/erase provides additional software protection. figure 23. ac waveforms for power transition v cc wp high we 3.3v device : ~ 2.5v 3.3v device : ~ 2.5v 100 s
flash memory 61 k9kag08u0m k9wbg08u1m k9ncg08u5m k9f8g08x0m is designed also to support the r ead for copy-back with data output to check a bit error for the controller which c an?t use the read edc status operation. the command sequences are as follows. figure a-1. (using data output) page copy-back program operation read for copy-back with data output timing guide figure a-1. (using data output) page copy-back program operation note : 1. copy-back program operation is allowed only within the same memory plane. "0" "1" 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h figure a-2. (using data output) page copy-ba ck program operation with random data input r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data 85h add.(2cycles) data 10h t prog 70h
flash memory 62 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b 85h 70h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 31 : must be same as previous a 31 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 31 : must be same as previous a 31 3 note3 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 0 ~ a 12 : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid 3 a 31 : valid a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 figure a-3. (using data output) two-plane copy-back program operation data field spare field (1) (3) plane0 source page target page (1) : two-plane read for copy back (2) : two-plane random data out (3) : two-plane copy-back program note : 1. copy-back program opera tion is allowed only within the same memory plane. 2 . any command between 11h and 81h is prohibited except 70h/f1h and ffh. (2) data field spare field (1) (3) plane1 source page target page (2)
flash memory 63 k9kag08u0m k9wbg08u1m k9ncg08u5m figure a-4. (using data output) two-plane copy-back program operation with random data input r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 3 4 4 destination address destination address note : 1. copy-back program operation is allo wed only within the same memory plane. 2. on the same plane, it?s prohibited to oper ate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). therefore, the copy-back program is permitted just between odd address pages or even address pages. 3 . any command between 11h and 81h is prohibited except 70h/f1h and ffh. note3 a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 31 : must be same as previous a 31 a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 31 : must be same as previous a 31 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 0 ~ a 12 : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid 3 a 31 : valid a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 a 31 : must be same as previous a 31
flash memory 64 k9kag08u0m k9wbg08u1m k9ncg08u5m 80h i/o 0 ~ 7 r/b 11h t dbsy address & data input address & data input t prog a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? note: any command between 11h and 80h is prohibited except 70h/f1h and ffh. note col add1,2 & row add 1,2,3 2112 byte data col add1,2 & row add 1,2,3 2112 byte data a 20 ~ a 30 : fixed ?low? a 19 : valid a 0 ~ a 12 : valid a 13 ~ a 18 : vaild a 20 ~ a 30 : valid a 19 : must be same with the previous 80h 10h 70h r/b 85h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 add.(5cycles) 00h r/b add.(5cycles) t r source address 35h i/ox col. add.1,2 & row add.1,2,3 1 col. add.1,2 & row add.1,2,3 1 destination address destination address a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : valid a 20 ~ a 30 : fixed ?low? a 31 : valid a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : must be same with the previous a 20 ~ a 30 : valid a 31 : must be same as previous a 31 11h note : 1. copy-back program opera tion is allowed only within the same memory plane. 2 . any command between 11h and 85h is prohibited except 70h/f1h/f2 and ffh. k9kag08u0m is designed also to support the program operation with 2kbyte data to offer the backward compatibility to the contro l- ler which uses the nand with 2kbyte p age. the command sequences are as follows. figure a-1. (2kb x 2) program operation figure a-2. (2kb x 2) copy-back program operation 2kb program operation timing guide a 31 : valid a 31 : must be same as previous a 31 t dbsy data output
flash memory 65 k9kag08u0m k9wbg08u1m k9ncg08u5m r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 00h r/b add.(5cycles) t r source address 35h i/ox col. add.1,2 & row add.1,2,3 1 r/b 85h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 1 2 2 destination address destination address note : 1. copy-back program operation is allowed only within the same memory plane. 2 . any command between 11h and 85h is prohibited except 70h/f1h/f2 and ffh. note2 a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : valid a 20 ~ a 30 : fixed ?low? a 31 : valid a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : must be same with the previous a 20 ~ a 30 : valid a 31 : must be same as previous a 31 figure a-3. (2kb x 2) copy-back program operation with random data input data output
flash memory 66 k9kag08u0m k9wbg08u1m k9ncg08u5m data field spare field (1) (6) plane0 source page target page (1) : two-plane read for copy back (2) : random data out on plane 0 (up to 4224byte) (3) : random data in on plane 0 (up to 4224byte) (4) : random data out on plane 1 (up to 4224byte) (5) : random data in on plane 1 (up to 4224byte) (6): two-plane program for copy back (2) (1) (6) plane1 source page target page (4) 4kbyte 4kbyte (3) (5) data field spare field col. add.1,2 60h i/o x r/b t prog a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b i/ox 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 12 : valid 2 r/b i/ox add(3 cycle) 60h add(3 cycle) 35h 00h add(5 cycle) 05h add(2 cycle) dout e0h up to 4224byte 85h add(5 cycle) din add(2 cycle) 11h 85h din col. add. 1,2 & row add.1,2,3 col. add.1,2 a 0 ~ a 12 : fixed ?low? a 13 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 21 : fixed ?low? a 0 ~ a 12 : valid 00h add(5 cycle) 05h add(2 cycle) dout e0h up to 4224byte t dbsy col. add.1,2 & row add.1,2,3 destination address a 0 ~ a 12 : valid a 13 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 31 : must be same as previous a 31 col. add.1,2 81h add(5 cycle) din add(2 cycle) 10h 85h din col. add.1,2 & row add.1,2,3 destination address a 0 ~ a 12 : valid a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 31 : must be same as previous a 31 2 note : 1. copy-back program operation is allo wed only within the same memory plane. t r 70h figure a-4. 2-plane copy-back program operation with ramdon data input a 31 : valid a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 a 31 : must be same as previous a 31 2-plane page program operation using 4kb buffer ram k9gag08x0m consists of 4kb pages and c an support two-plane program operation. the in ternal ram requirement for a controller is 8kb, but for those controllers which support less than 8kb ram, the following sequence can be used for two-plane program ope r- ation.
flash memory 67 k9kag08u0m k9wbg08u1m k9ncg08u5m wp ac timing guide enabling wp during erase and program busy is progibited. the erase and program operations ar e enabled and disabled as follows: figure 24. program operation 1. enable mode 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode 80h 10h we i/o wp r/b tww(min.100ns) 1. enable mode 60h d0h we i/o wp r/b tww(min.100ns) 2. disable mode 60h d0h we i/o wp r/b tww(min.100ns) figure 25. erase operation

▲Up To Search▲

Price & Availability of K9WBG08U1M-ICB00

	To Download K9WBG08U1M-ICB00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .